1. Field of the Invention
The present invention relates to a method for detecting a correlation between digital signals using a spectrum communication system for pocket telephones and a matched filter unit that uses the correlation detecting method.
2. Description of the Related Art
At first, a configuration of a related art matched filter unit will be described with reference to FIG. 16. FIG. 16 shows a configuration of the first related art matched filter unit used for receiving signals from two 5-time diffusion 5-tap channels, each composed of an FIR digital filter.
This related art matched filter unit is provided with input terminals 1 and 2, a clock signal input terminal 3, a shift register 9 composed of five delay circuits 4 to 8 disposed in five stages, a shift register 15 composed of five delay circuits 10 to 14 disposed in five stages, multipliers 16 to 25, adders 26 and 27, and output terminals 28 and 29. Each of the multipliers 16 to 20 uses corresponding one of the code values in a back-diffusion code string C4C3C2C1C0 for the digital signal I. Each of the multipliers 21 to 25 uses corresponding one of the code values in a back-diffusion code string C04C03C02C01C00 for the digital signal Q.
This related art matched filter unit provides each channel with a correlation detecting circuit. Since the matched filter unit has two channels, it is provided with two matched filters 30 and 31. The matched filter 30 corresponding to the digital signal I is provided with a shift register 9 composed of five delay circuits 4 to 8 disposed in five stages, multipliers 16 to 20, and an adder 26. In the same way, the matched filter 31 corresponding to the digital signal Q is provided with a shift register 15 composed of five delay circuits 10 to 14 disposed in five stages, multipliers 21 to 25, and an adder 27.
The input terminals 1 and 2 receive the digital signals I and Q obtained by sampling analog signals (for example, spectrum diffusion signals) with a 4.096 MHz sampling frequency. The digital signals I and Q are synchronized with a 4.096 MHz clock signal CLK entered to the clock signal input terminal. The digital signal I is entered to the first delay circuit 4 of the shift register 9, then shifted from the first delay circuit 4 to the fifth delay circuit 8 sequentially in synchronization with the clock signal CLK. In the same way, the digital signal Q is entered to the first delay circuit 10 of the shift register 15, then shifted from the first delay circuit 10 to the fifth delay circuit 14 sequentially in synchronization with the clock signal CLK.
The multiplier 16 multiplies a signal output from the first delay circuit 4 of the shift register 9 by the back-diffusion code value C0 of the back-diffusion code string C4C3C2C1C0. Each of the multipliers 17 to 20 multiplies a signal output from corresponding one of the delay circuits 5 to 8 by corresponding one of the back-diffusion code values C1 to C4. Each of the multipliers 21 to 25 multiplies a signal output from corresponding one of the delay circuits 10 to 14 by corresponding one of the back-diffusion code values C00 to C04.
The adder 26 receives and adds the result of multiplication performed in each of the multipliers 16 to 20, while the adder 27 receives and adds the result of multiplication performed in each of the multipliers 21 to 25. Consequently, a value of the correlation with the entered digital signal I is output to the output terminal 28 and a value of correlation with the entered digital signal Q is output to the output terminal 29.
Next, description will be made for a procedure of multiplication performed in each of the multipliers 16 to 25, as well as a procedure of back-diffusion computing performed in each of the adders 26 and 27 with reference to the timing chart shown in FIG. 17.
In the initial state, all the signals output from the delay circuits 4 to 8 and 10 to 14 composing the shift registers 9 and 15 respectively are set in the low level.
At first, in the first operation state of the matched filter 30, the first sampling data D0 of the digital signal I is entered to the input terminal 1 synchronously with the clock signal CLK, then fetched into the first delay circuit 4. The multiplier 16 multiplies this sampling data D0 by the back-diffusion code value C0. Consequently, the multiplier 16 outputs a signal indicating the value D0xc3x97C0.
In the second operation state, the second sampling data D1 of the digital signal I is entered to the input terminal 1 synchronously with the clock signal CLK, then fetched into the first delay circuit 4. At the same time, the first sampling data D0 is fetched into the second delay circuit 5. Consequently, the multiplier 16 multiplies the second sampling data D1 by the back-diffusion code value C0 and the multiplier 17 multiplies the first sampling data D0 by the back-diffusion code value C1. The multiplier 16 thus outputs a signal indicating the value D1xc3x97C0 and the multiplier 17 outputs a signal indicating the value D0xc3x97C1. Hereafter, the same processings are repeated until the fourth sampling data D3 is entered to the input terminal 1.
After this, if the fifth sampling data D4 of the digital signal I is entered to the input terminal 1 synchronously with the clock signal CLK entered to the clock signal input terminal 3, the first to fifth sampling data D0 to D4 are fetched into the delay circuits 4 to 8 respectively. Consequently, the multiplier 16 outputs the result of multiplication indicating the value D4xc3x97C0 and the multiplier 17 outputs the result of multiplication indicating the value D3xc3x97C1. And, the multiplier 18 outputs the result of multiplication indicating the value D2xc3x97C2, the multiplier 19 outputs the result of multiplication indicating the value D1xc3x97C3, and the multiplier 20 outputs the result of multiplication indicating the value D0xc3x97C4. This completes all the necessary processings for finding a correlation value between the back-diffusion code string C4C3C2C1C0 and the first five sampling data D0 to D4 of the digital signal I. The adder 26 adds the multiplication result from each of the multipliers 16 to 20 and outputs the correlation result H (4) from the output terminal 28.
The same processings are also performed in the matched filter 31. The first five sampling data D00 to D04 of the digital signal Q are entered to the input terminal 2. Each of the multipliers 21 to 25, as well as the adder 27 performs a back-diffusion computing processing with respect to the back-diffusion code string C04C03C02C01C00 and the correlation result H (04) is output from the output terminal 29. Hereafter, the same processings are repeated.
Next, description will be made for another related art matched filter unit used when a received signal is over-sampled.
When a receiving timing of a received signal is detected by detecting the correlation with the received signal for a pocket telephone, the received signal is usually over-sampled by m times with respect to the chip rate frequency, then it is entered to a matched filter unit. This is to improve the accuracy of detecting the receiving timing.
FIG. 18 is a configuration of the second related art 5-time diffusion 10-tap matched filter unit composed of FIR digital filters.
This related art matched filter unit is provided with input terminals 101 and 102, a clock signal input terminal 103, a shift register 109 composed of delay circuits 104 to 108 disposed in five stages, a shift register 115 composed of delay circuits 110 to 114 disposed in 10 stages, multipliers 116 to 125, adders 126 and 127, and output terminals 128 and 129. Each of the multipliers 116 to 120 uses corresponding one of the code values of the back-diffusion code string C4C3C2C1C0 for the digital signal I, while each of the multipliers 121 to 125 uses corresponding one of the code values of the back-diffusion code string C04C03C02C01C00 for the digital signal Q.
Just like the first related matched filter unit, this second related art matched filter unit provides each channel with one correlation detecting circuit. Since this related art second matched filter unit has two channels, it is provided with two matched filters 130 and 131.
To the input terminals 101 and 102 are entered digital signals I and Q generated by sampling analog signals (for example, spectrum diffusion signals) with a 8.192 MHz sampling frequency (double the sample frequency in the above one). The digital signals I and Q are synchronized with the 8.192 MHz clock signal CLK entered to the clock signal input terminal 103. The digital signal I is entered to the first delay circuit 104 of the shift register 109, then shifted from the first delay circuit 104 to the fifth delay circuit 108 sequentially in synchronization with the clock signal CLK. Each of the delay circuits 104 to 108 is a two-stage delay circuit in this embodiment. Each delay circuit takes about 2 clocks to shift signal data to the next delay circuit. In the same way, the digital signal Q is entered to the first delay circuit 110 of the shift register 115, then shifted from the first delay circuit 110 to the fifth delay circuit 114 sequentially in synchronization with the clock signal CLK.
The multiplier 116 multiplies a signal output from the first delay circuit of the shift register 109 by the back-diffusion code value C0 of the back-diffusion code string C4C3C2C1C0. Each of the multipliers 117 to 120 multiplies a signal output from each of the delay circuits 105 to 108 by corresponding one of the back-diffusion code values C1 to C4. Each of the multipliers 121 to 125 multiplies a signal output from each of the delay circuits 110 to 114 by corresponding one of the back-diffusion code values C00 to C04.
The adder 126 receives and adds results of multiplication from the multipliers 116 to 120, while the adder 127 receives and adds results of multiplication from the multipliers 121 to 125. Consequently, a value of correlation with respect to the entered digital signal I is output to the output terminal 128 and a value of correlation with respect to the entered digital signal Q is output to the output terminal 129.
Furthermore, since such a value of correlation with respect to each of the digital signals I and Q is obtained in the matched filter unit shown in FIG. 8 each time a 8.196 MHz clock CLK is entered to the clock signal input terminal 103, the matched filter unit shown in FIG. 18 can obtain a value of correlation at a xc2xd time interval of that of the matched filter unit shown in FIG. 16.
In the configurations of the first and second related art matched filter units described above, however, each channel needs a matched filter. When the spectrum communication method for pocket telephones is adopted, therefore, a matched filter is needed for each of the two channels (same phase channel and orthogonal channel). In addition, if the object matched filter unit has a space diversity, a matched filter is needed for each of the four channels in total. And, this makes it expand the circuitry size of the matched filter unit. This is why the related art matched filter units described above have suffered from a problem that it is difficult to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
Under such the circumstances, it is an object of the present invention to provide a correlation detecting method and a matched filter unit that uses the correlation detecting method, which can solve the above related art problems and can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites for detecting a correlation between diffusion-modulated digital signals entered from a plurality of channels.
The correlation detecting method of the present invention is used to find a value of correlation between each of a plurality of digital signals and each of a plurality of digital code strings. The correlation detecting method includes a process for multiplexing a plurality of the digital signals, a process for storing each of multiplexed signals, and a process for a back-diffusion computing processing of each of those stored multiplexed signals and a plurality of the digital code strings.
According to the present invention, therefore, a plurality of digital signals that are diffusion-modulated with different code values are not correlative with each other and those non-correlative digital signals are multiplexed and stored. Then, each of the stored multiplexed signals is computed for back-diffusion using each of a plurality of the digital code strings, so that the same storage circuit can be used to detect a correlation between digital signals (both I and Q) entered from a plurality of channels. This is why it is possible to provide a matched filter unit that can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
The matched filter unit of the present invention is used to find a value of correlation between each of a plurality of digital signals synchronized with a clock and each of a plurality of digital code strings consisting of M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for multiplexing a plurality of digital signals, a storage circuit composed of delay circuits disposed in M (M: plural) stages and used for entering a signal from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the clock, and a plurality of computing devices used respectively for finding a value of correlation between each of a plurality of the digital signals and a digital code string using a signal output from corresponding one of the delay circuits disposed in M stages. Each of the computing devices is provided with M (M: plural) multipliers, each used for multiplying a signal output from the corresponding delay circuit by each digital code of a digital code string, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
Furthermore, the matched filter unit of the present invention is also used to find a value of correlation between each of a plurality of digital signals over-sampled with the second clock having a frequency m times that of the first clock and each of a plurality of digital code strings consisting of M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for multiplexing a plurality of digital signals, a storage circuit composed of delay circuits disposed in mxc3x97M stages and used for entering a signal output from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the second clock, and a plurality of computing devices used respectively for finding a value of correlation between each of a plurality of the digital signals and a digital code string using a signal output from each m-th stage delay circuit of the delay circuits disposed in mxc3x97M stages. Each of the computing devices comprises M (M: plural) multipliers used respectively for multiplying a signal output from each m-th stage delay circuit and each digital code of a digital code string, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
According to those inventions, a plurality of digital signals that are diffusion-modulated with different code values are not correlative with each other and those non-correlative digital signals are multiplexed. Then, each multiplexed signal is computed for back-diffusion in the storage circuit, the multiplier, and the adder using a digital code string different from those of other multiplexed signals, so that the same storage circuit can be used to detect a correlation between digital signals (both I and Q) entered from a plurality of channels. This is why the present invention can provide a matched filter unit that can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
The correlation detecting method of the present invention is used to find a value of correlation between each of a plurality of digital signals and each of a plurality of digital code strings. The correlation detecting method includes a process for multiplexing a plurality of digital signals, a process for storing each of multiplexed signals, a process for switching a plurality of digital code strings in a time-dividing manner, and a process for performing a back-diffusion computing processing for each of the stored multiplexed signals and the digital code strings switched in a time-dividing manner.
According to the present invention, a plurality of digital signals that are diffusion-modulated with different code values are not correlative with each other and those non-correlative digital signals are multiplexed and stored. And, each of those stored multiplexed signals is computed for back-diffusion in time-dividing manner, so that the same storage circuit and the same back-diffusion computing device can be used to detect a value of correlation between digital signals (both I and Q) entered from a plurality of channels. Consequently, the present invention can provide a matched filter unit that can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
The matched filter unit of the present invention is used to find a value of correlation between each of a plurality of digital signals synchronized with a clock and each of a plurality of digital code strings consisting of M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for multiplexing a plurality of digital signals, a storage circuit composed of delay circuits disposed in M (M: plural) stages and used for entering a signal from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the clock, a circuit for switching a plurality of digital code strings to output in a time-dividing manner, M (plural) multipliers used respectively for multiplying a signal output from each delay circuit by each digital code of a digital code string output from the digital code string switching circuit, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
Furthermore, the matched filter unit of the present invention is also used to find a value of correlation between each of a plurality of digital signals over-sampled with the second clock having a frequency m times that of the first clock and each of a plurality of digital code strings consisting of M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for multiplexing a plurality of digital signals, a storage circuit composed of delay circuits disposed in mxc3x97M stages and used for entering a signal output from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the second clock, a circuit for switching a plurality of digital code strings to output in a time-dividing manner, and M (M: plural) multipliers used respectively for multiplying a signal output from each m-th stage delay circuit of the delay circuits disposed in mxc3x97M stages, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
According to those inventions, a plurality of digital signals that are diffusion-modulated with different code values are not correlative with each other and those non-correlative digital signals are multiplexed. Then, each multiplexed signal is computed for back-diffusion in the same storage circuit, the same multiplier, and the same adder in a time-dividing manner using a digital code string switched in a time-dividing manner in the digital code string switching circuit, so that the same storage circuit, the same multiplier, and the same adder can be used to detect a correlation between digital signals (both I and Q) entered from a plurality of channels. This is why the present invention can provide a matched filter unit that can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
The correlation detecting method of the present invention is used to find a value of correlation between each of a plurality of digital signals and each of a plurality of digital code strings. The correlation detecting method includes a process for changing a phase of a plurality of digital signals, a process for multiplexing a plurality of the digital signals including those whose phase is changed, a process for storing each of multiplexed signals, a process for performing a back-diffusion computing processing for each of the stored multiplexed signals and a plurality of the digital code strings.
According to the present invention, a phase of a plurality of digital signals that are diffusion-modulated with the same code value is changed thereby to eliminate each correlation between a plurality of the digital signals, then those non-correlative digital signals are multiplexed and stored. After this, each of the stored multiplexed signals is computed for back-diffusion, so that the same storage circuit and the same back-diffusion computing device are used to detect each correlation between a plurality of the digital signals. This is why the present invention can provide a matched filter unit that can be reduced significantly in circuitry size to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.
The matched filter unit of the present invention is used to find a value of correlation between each of a plurality of digital signals synchronized with a clock and a digital code string consisting M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for changing a phase of a plurality of digital signals, a circuit for multiplexing a plurality of the digital signals including those whose phase is changed, a storage circuit composed of delay circuits disposed in M (M: plural) stages and used for entering a signal from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the clock, M (plural) multipliers used respectively for multiplying a signal output from each delay circuit by each digital code of a digital code string output from the digital code string switching circuit, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
Furthermore, the matched filter unit of the present invention is also used to find a value of correlation between each of a plurality of digital signals over-sampled with the second clock having a frequency m times that of the first clock and each of a plurality of digital code strings consisting of M (M: plural) digital codes respectively. The matched filter unit comprises a circuit for changing a phase of a plurality of digital signals, a circuit for multiplexing a plurality of the digital signals including those whose phase is changed, a storage circuit composed of delay circuits disposed in mxc3x97M stages and used for entering a signal output from the signal multiplexing circuit to the first stage delay circuit, then shifting the signal to the subsequent delay circuits sequentially in synchronization with the second clock, M (M: plural) multipliers used respectively for multiplying a signal output from each m-th stage delay circuit of the delay circuits disposed in mxc3x97M stages, and an adder for adding results of multiplication from the M multipliers to find a value of correlation.
According to those inventions, a phase of a plurality of digital signals that are diffusion-modulated with the same code value is changed thereby to eliminate each correlation between those digital signals, then those digital signals are multiplexed. After this, each of multiplexed signals is computed for back-diffusion in the storage circuit, the computing device, and the adder using a digital code string, so that the multiplexed signal is computed for back-diffusion in the storage circuit, the multiplier, and the adder using a digital code string, so that the same storage circuit, the same multiplier, and the same adder can be used to detect a correlation between digital signals (both I and Q) entered from a plurality of channels. This is why the present invention can provide a matched filter unit that can be reduced significantly in circuitry size thereby to satisfy the miniaturizing, lower manufacturing cost, and power saving prerequisites.